1. Field of the Invention
The present invention relates to a self-repair method for nonvolatile memory devices with erasing/programming failure, and a relative nonvolatile memory device.
2. Description of the Related Art
As is known, in a semiconductor multimegabit nonvolatile memory device (EPROM or flash), the cell array constitutes a substantial fraction, accounting for between 40% and 70% of the total area. The applications for which nonvolatile memories are designed require a perfect functionality of all the cells in the array during the operative steps of the device (reading, programming and erasing).
In theory, the presence of at least one cell that does not operate correctly is sufficient for the entire memory device to be unusable. This condition is of considerable importance during industrial fabrication of this type of integrated device, in so far as there exists a non-zero likelihood of failure of a memory cell in any given production lot.
In the absence of solutions for detecting and correcting failure bits, the likelihood of having devices with perfectly operating memory cells in a given production lot would be very low and hence unacceptable from the point of view of large-scale industrial production. This likelihood indicates the so-called “prime yield” of the lot and represents a figure of merit of the production process.
In order to increase the yield of memory devices in the final manufacture steps, circuit solutions have been employed for recognizing and correcting the failure bits. A technique commonly adopted for this purpose uses memory cells additional to the ones making up the memory array and designed to replace corresponding failed array cells. The cells used, defined as redundant or redundancy cells, are identical to the array cells. They must be appropriately managed by circuits additional to the ones already normally present inside the device.
In particular, the organization of the memory favors the use of entire rows or entire columns made up of redundant cells, such as to replace corresponding rows or columns of the array even in the presence of just one failed cell. In this way, a compromise is reached between the power for correcting the failures and the area required for the circuits managing the redundancy.
Usually, activation of redundancy occurs during the electrical-wafer sorting (EWS) step, during which, through an appropriate test flow, the cells that present some problem are identified and replaced with the redundancy cells. The redundancy, whether row redundancy or column redundancy, is thus able to correct only the defects that occur at time zero, i.e., in the factory.
For instance, should a sensible reduction in gain arise for a given cell, on account of cycling, the cell could no longer be able to get over the erasing and programming steps, so causing failure of the entire device.